1. Field of the Invention
The present invention relates to a semiconductor memory. In particular, it relates to the semiconductor memory having a plurality of Static Random Access Memory (SRAM) cells configured by Fin Field Effect Transistors (Fin FETs).
2. Description of the Related Art
Recently, as for the semiconductor device such as LSI, high performance has been achieved by the miniaturization of the used device. In the scaling of the device, the gate length is reduced on the basis of a so-called scaling law, and the gate insulator is made thin film, in a Metal-Oxide Semiconductor Field-Effect Transistor (MOSFET) used for a logic circuit in a semiconductor device and a memory unit of Static Random Access Memory (SRAM) etc.
And then, a Fin FET that is Fully Depleted MOSFET of double-gate type is proposed in order to improve the cutoff characteristic that decreases by the short-channel effect occurred by the transistor whose gate length L is less than 30 nm (e.g., see Japanese patent Laid Open Publication No. H02-263473).
The Fin FET is a kind of three dimensional MIS type semiconductor device, and the channel can be formed to the side view of the fin on two surfaces by forming projection fin (Fin) that thinly excises silicon (Si) layer like the strip of paper, and making this fin overpass by the gate electrode. As for this Fin FET, the channel region of the fin FET is completely made depleted. Therefore, when a general-purpose Poly-Silicon layer was used for the gate electrode, it was difficult to set the threshold voltage to the low threshold voltage (for example, 0.2V or less in the absolute value) in which it aimed at the high current drive.
When it tries to configure the circuit of Static Random Access Memory Cell (SRAM Cell) by using such the Fin FET, the threshold voltage of the Fin FET cannot be properly controlled and the channel width cannot be set arbitrarily. Therefore, there was a problem with a difficult setting of the current transfer ratio of each Fin FET to a proper value. As a result, since it was difficult for the SRAM Cell to obtain enough a Static Noise Margin (SNM), the operational biasing point might be unstable, and it might be weak also to soft-error, etc., (e.g., see, E. J. Nowak, et al., “A Functional Fin FET-DGCMOS SRAM Cell”, International Electron Devices Meeting (IEDM), Tech. Dig., IEEE, 2002, p. 411-414).
Moreover, the control of the potential of the channel region is performed in order to obtain the low threshold voltage in which it aims at the high current drive by the Fin FET (e.g., see, Y. X. Liu, et al, “Flexible Threshold Voltage Fin FETs with Independent Double-gates and an Ideal Rectangular Cross-Section Si-Fin Channel”, International Electron Devices Meeting (IEDM), Tech. Dig., IEEE, 2003, p. 986-989).
The Fin FET in the above paper is called as a back-gate type MOSFET. Since the additional electrode layer for the control of the potential of the channel region was newly needed, the SRAM cell with the layout that embedded the back-gate type Fin FET was not created.